The invention relates generally to electronic interface circuits and deals more particularly with a bidirectional level shifting interface circuit for use between two different digital circuits operating at different voltage levels.
Many systems utilize two different circuit technologies which operate with a common ground (binary zero level) but different binary one or high voltage levels. Such circuits require an interface to permit bidirectional communication between the two circuits. For example, new CMOS technology operates at lower voltage than older CMOS technologies to improve performance and density. However, it may be advantageous in some applications to provide in one system a combination of both technologies. In such a system, each printed circuit board or other circuit carrying card typically contains only one technology and is connected by a transmission line to another board or card containing a different technology. If one of the CMOS technologies operates between 3.4 volts and ground and the other operates between 5 volts and ground, a 3.4 volt binary one signal from the first technology cannot reliably drive the second technology. This is because the second technology can have a maximum 3.1 volt threshold and there are losses in greater margin of drive voltage. Also, if a 5 volt signal were applied directly to the 3.4 volt receiver, the 5 volt signal could breakdown the 3.4 volt receiver. Thus, an interface is required to drive the respective receiving circuit with a proper voltage level.
Heretofore it was known to provide a level shifting transceiver between the two circuit boards to provide the appropriate voltage for each technology and a non-level shifting transceiver at the I/O of each circuit. Such a level shifting transceiver comprises two buffer gates connected in opposite directions back-to-back, and an inverter gate to enable one buffer gate while disabling the other (to provide a high impedance output) depending on the direction of communication. One of the buffer gates was biased at the 5 volt level and the other buffer gate was biased at the 3.4 voltage level. However, there are problems with such a level shifting transceiver because it requires a separate enable signal and adds a propagation delay through the respective buffer gate.
U.S. Pat. No. 4,216,390 to Stewart discloses a unidirectional level shifting circuit which comprises an N Channel FET. A source of the FET Channel is connected to first relatively low voltage digital circuit via a first inverter circuit, and a drain of the FET Channel is connected to a second relatively high voltage digital circuit via a second inverter circuit. Thus, a relatively low voltage, binary one communication signal of the first digital circuit passes through the first inverter circuit, the channel of the FET and the second inverter circuit to the output of the level shifting circuit. This output is also connected to an input of a first latch and the output of the first latch is connected to the input of the second inverter circuit. Thus, when the relatively low voltage binary one signal passes to the output of the level shifting circuit, it is latched to the relatively low voltage. This level shifting circuit also includes another FET which has its source connected to the high voltage supply and its drain to the second inverter. This FET is activated by a separate enable signal to deliver the relatively high voltage to the output of the level shifting circuit via the second inverter after the relatively low voltage passes to the output of the level shifting circuit.
A general object of the present invention is to provide a bidirectional level shifting interface circuit for use between two different circuits operating at different voltage levels.
A more specific object of the present invention is to provide an interface circuit of the foregoing type which introduces a minimal propagation delay therethrough.
Another specific object of the present invention is to provide an interface circuit of the foregoing type which does not require an enable or other control signal to operate.